The present invention relates to a method of manufacturing a semiconductor device wherein an active region with MOS transistors mounted thereon is partitioned with a trench isolation.
With the recent tendency toward higher integration and increasing miniaturization of an LSI with semiconductor elements mounted thereon, there has been undertaken the study of trench isolation as a method of electrically isolating the individual semiconductor elements. The trench isolation is promising as a replacement for the LOCOS process which is predominantly used at present. According to the trench isolation, a trench is formed to surround regions in which the respective semiconductor elements are to be formed (element formation regions) and an insulating film is filled in the trench, thereby forming isolation. The following is the reason that the trench isolation has been studied as the replacement for the LOCOS process.
Since the LOCOS process involves selective oxidation of a silicon substrate, the bird's beak phenomenon occurs at the ends of a mask covering the element formation regions for preventing the oxidization thereof. The resulting insulating film intrudes into the element formation regions, which causes variations in size. The LOCOS process is also disadvantageous in that, as a further reduction is achieved in the spacing between the semiconductor elements, the rate at which oxygen is supplied is controlled. As a result, the insulating film becomes thinner in the element formation region with a smaller width than in the element formation region with a larger width, which degrades the isolating function.
On the other hand, the trench isolation is structurally free from the problem of the bird's beak and does not involve the selective oxidization process, so that the thinning of the insulating film due to the controlled oxygen supply rate does not occur. For this reason, the trench isolation is becoming prevalent in LSI fabrication with 0.5-.mu.m design rules or under.
Below, a description will be given to a method of manufacturing a semiconductor device using conventional trench isolation. FIGS. 11(a) to 11(f) are cross sectional views illustrating procedures for forming trench isolation in a semiconductor device of relatively low integration.
Initially, as shown in FIG. 11(a), a silicon dioxide film 11 and a silicon nitride film 12 are deposited on a semiconductor substrate 10. After that, an opening corresponding to an isolation region Rto is formed in the silicon nitride film 12 and a photoresist film FR1 is formed to cover element formation regions Rtr.
Next, as shown in FIG. 11(b), etching is performed using the above photoresist film FR1 as a mask so as to selectively remove the silicon nitride film 11, the silicon dioxide film 11, and the semiconductor substrate 10, thereby forming a trench 10a. In this process, etching conditions are determined so that the angle .theta. between the surface of the semiconductor substrate 10 and the side face of the trench 10a, which is defined as a taper angle, has a value larger than 90', i.e., so that the trench 10a is inwardly tapered at a large taper angle .theta.. Next, as shown in FIG. 11(c), the photoresist film FR1 is removed and then a silicon dioxide film with a thickness larger than the depth of the trench 10a is deposited by vacuum CVD so as to compose an insulating film 31 for isolation, with which the trench 10a is filled.
Next, as shown in FIG. 11(d), the substrate surface is planarized using, e.g., chemical mechanical polishing (hereinafter referred to as CMP). As a result, the insulating film 31 for isolation is completely removed from the element formation regions Rtr, thereby exposing the surface of the silicon nitride film 12. At this stage, the insulating film for isolation remaining in the trench 10a forms isolation 31a. Alternatively, there has also been used a method of forming the inverted pattern of the element formation regions Rtr from the photoresist film and performing etch back using the inverted pattern.
Next, as shown in FIG. 11(e), the silicon nitride film 12 is removed using, e.g., hot phosphoric acid and the silicon dioxide film 11 is subsequently removed using, e.g., a wet etching agent containing hydrofluoric acid as the main component, thereby completing the process of forming the isolation.
Next, as shown in FIG. 11(f), a polysilicon film is deposited on the substrate by a well-known method via a gate insulating film 16 composed of a silicon dioxide film. The polysilicon film is then patterned into gate electrodes 17a. Thereafter, such process steps as forming source/drain regions by ion implantation of an impurity, depositing an interlayer insulating film, forming contact holes in the interlayer insulating film, and forming upper metal interconnections are sequentially performed, though the drawing thereof is omitted, thereby finishing the semiconductor device.
In the above conventional method of manufacturing a semiconductor device, the taper angle .theta. between the side face of the trench 10a and the surface of the semiconductor substrate 10 is set at a value much larger than 90', thereby implementing the inwardly tapered trench 10a with considerably steep side faces. This is for preventing a so-called shadowing effect in consideration of unsatisfactory step coverage of the silicon dioxide film composing the insulating film for isolation.
However, with higher integration of a semiconductor device, not only the element formation regions Rtr but also the isolation region Rto is reduced in size, which causes the following problems.
FIGS. 12(a) to 12(f) are cross sectional views illustrating the manufacturing process in the case of reducing the spacing between the semiconductor elements, i.e., the width of the isolation region Rto. The respective steps shown in FIGS. 12(a) to 12(f) are identical with those shown in FIGS. 11(a) to 11(f). Among these, FIG. 12(a) shows the step of forming the inwardly tapered trench 10a with its width gradually decreasing toward the bottom thereof. In this case, since the width of the isolation region Rto has been reduced, the taper angle .theta. inevitably approaches 90'. In other words, the taper angle .theta. is inevitably reduced rather than increased. Otherwise, the width of the bottom portion of the isolation 10a, which has been reduced together with the width of the isolation region Rto, may become excessively small because of the increased taper angle .theta.. In serious cases, the side faces interfere with each other at the bottom to present a triangular profile, which reduces the depth of the trench 10a and therefore inhibits the isolating function.
As a result of thus increasing an aspect ratio by reducing the width of the trench 10a and reducing the taper angle .theta. of the trench 10a, the probability of a void 19 being formed in the silicon dioxide film 31 becomes extremely high, as shown in FIG. 12(c), due to the shadowing effect. If the void 19 is opened in the planarized surface of the substrate, as shown in FIG. 12(d), the polysilicon composing the gate electrodes is filled in the void 19 in the subsequent step shown in FIG. 12(f). Since the vertical position in which the void is formed varies, the void 19 may not be opened in the step shown in FIG. 12(d), but it has a high possibility of being opened during the subsequent step. Referring now to FIG. 13(a), a description will be given to the relationship between the vertical position and formation possibility of the void. Although a void 19x shown in FIG. 13(a) is in a comparatively low position, it is opened at the time when the silicon nitride film 12 and silicon dioxide film 11 are removed in the step shown in FIG. 12(e), since the silicon dioxide film composing the isolation 31a is also removed to a certain extent (e.g., about 10 to 30 nm). In short, if the upper edge of the void 19x is higher in position than the surface of the isolation 31a which is defined in the subsequent step, as shown in FIG. 13(b), it is inevitably opened.
Although a large number of voids 19 apparently exist in the cross sectional views, they are actually connecting to each other, as can be seen from the plan view of FIG. 14. Accordingly, if a polysilicon film is deposited over the void to form the gate electrodes, the polysilicon film remains in the void, as shown in FIG. 12(f), so that the gate electrodes are shortcircuited via the polysilicon film remaining in the void. Even if it is supposed that the void is not opened in every cross section, reliability is degraded.